SoC Design Validation Engineer San Jose, CA
Saige Partners is looking for a SoC Design Validation Engineer to join one of our top clients in the San Jose, CA area on a full time basis. As a member of the GNSS ASIC team, the candidate will contribute the SoC design/Validation with architecture, systems and digital RF and optimize the GNSS products. It is required to have strong background on implementation of low power wireless SoC design experience. The candidate should exhibit strong technical abilities and collaboration with other team members across worldwide location, and great communication skills in spoken and written language.
As an SoC Design/Validation engineer you will have responsibilities spanning all aspects of SoC:
- Will be responsible for chip level design infrastructure.
- Integrate/Validate both internal and external IPs.
- Responsibility includes feasibility, micro-architecture, RTL design, design validation, front-end implementation and post-silicon system bring-up.
REQUIRED SKILLS (Education Certificates, Licenses, Travel)
The ideal candidate will have 5+ years of experience in low power wireless SoC design with a leading chipset company:
- BS with extensive industry experience or MS is preferred.
- Previous design and validation experience in IP level and SoC level.
- Industry exposure to and knowledge of SoC design methodology.
- Experience with system design methodologies that contain multiple clock domains.
- Experience in clock, power management and system debug designs.
- Experience in low-power design issues, tools, methodologies, and power analysis capabilities.
- Excellent collaboration skills
- Outstanding written and verbal communication